Full-Time Principal Engineer, VLSI Design Engineering

• Synthesis and DFT scan insertionFamiliar timing constraint and qualify, clean up timing constraints file in Synthesis.
• Be able to timing and DFT analysis to improve Synthesis and DFT coverage performance.
• Place and RoutingPlacement stage timing and routing analysis and improvement.
• CTS: Clock tree analysis, adjust clock skew, insertion delay to improve clock tree quality and timing.
• Routing: be able to debug and analysis timing, routing issue in routeOpt stage,STA timing analysis
• MMMC timing analysis using PT and fix timing in PNR.
• Timing ECO flow using PrimeClosure.
• DRC/LVS/Antenna verificationVerify DRC/LVS/Antenna in PNR and Layout and fix violations.
• Team work and Communication:Good team work with team member and others function team.
• Good communications skill.

• Experience: A minimum of 10 years in Physical design digital RTL to GDS flow.
• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• Programming & Scripting: Proficiency in TCL/TK, Perl scripting.
• EDA Tools: Familiarity with Cadence, Synopsys digital flow include Synthesis, PNR, STA. Calibre physical verification, Redhawk power analysis.

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